劉大江

深度強化學習、軟件定義硬件、深度學習編譯、可重構計算 ^[1] 

他分別於2009、2015年在電子科技大學和清華大學獲得學士、博士學位；2015年8月-2017年8月在清華大學計算機系從事博士後研究工作；2017年9月至2019年12月在重慶大學計算機學院任職講師，2020年1月至今在重慶大學計算機學院任職副教授；2018年7月曾在澳大利亞昆士蘭大學和悉尼科技大學訪問交流。 ^[1] 

曾獲教育部科技成果完成者證書。曾帶隊參加世界大學生超級計算機競賽ASC19並獲得二等獎。 ^[1] 

(1) D. Liu#*, S. Yin, G. Luo, J. Shang, L. Liu, S. Wei, Y. Feng and S. Zhou. Data-Flow Graph Mapping Optimization for CGRA with Deep Reinforcement Learning, IEEE Trans. on Computer-Aided Design (TCAD) of Integrated Circuits and Systems, 2018 (Article in press)

(2) D. Liu#, S. Yin, Y. Peng, L. Liu, and S. Wei. Optimizing spatial mapping of nested loop for coarse-grained reconfigurable architectures. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 23(11): 2581-2594, 2015

(3) D. Liu#, S. Yin, L. Liu, and S. Wei. Mapping multi-level loop nests onto CGRAs using polyhedral optimizations. IEICE TRANSACTIONS on Fundamentals, 98-A(7): 1419-1430, 2015.

(4) D. Liu#, S. Yin, C. Yin, L. Liu, and S. Wei. Mapping optimization of affine loop nests for reconfigurable computing architecture. IEICE transactions on electronics, E95-D(12):1284–1290, 2012.

(5) S. Yin, D. Liu, Y. Peng, L. Liu, and S. Wei. Improving nested loop pipelining on coarse-grained reconfigurable architectures. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 24(2): 507-520, 2016.

(6) S. Yin, D. Liu, L. Liu, and S. Wei. Affine transformations for communication and reconfiguration optimization of mapping loop nests on CGRAs. IEICE Transactions on INF. & SYST. 96-D(8): 1582-1591, 2013.

(7) S. Yin, X. Yao, D. Liu, L. Liu, and S. Wei. Memory-aware loop mapping on coarse-grained reconfigurable architectures. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 24(5): 1895-1908 (2016).

(1) D. Liu#, S. Yin, L. Liu, and S. Wei. Polyhedral model based mapping optimization of loop nests for CGRAs. in Proc. 50th ACM/EDAC/IEEE Design Autom. Conf.(DAC), May/Jun. 2013, pp. 1–8.

(2) S. Yin, D. Liu, L. Liu, and S. Wei. Joint affine transformation and loop pipelining for mapping nested loop on CGRAs. Proceedings of Design, Automation Test in Europe Conference Exhibition (DATE), 2015. IEEE, 2015, pp. 115–120.

(3) S. Yin, D. Liu*, L. Sun, X. Liu, and S. Wei. Learning convolutional neural networks for data-flow graph mapping on spatial programmable architectures. Field-Programmable Gate Arrays(FPGA),25th ACM/SIGDA International Symposium on, February 22-24, 2017: 295

(4) D. Liu, S. Yin, L. Liu, and S. Wei. Affine transformations for communication and reconfiguration optimization of loops on CGRAs. Circuits and Systems (ISCAS), Proceedings of 2013 IEEE International Symposium on. IEEE,2013, pp. 2541-2544

(5) S. Yin, D. Liu, L. Sun, L. Liu, X. Lin, and S. Wei. DFGNet: Mapping data-flow graph onto CGRA by a deep learning approach. Circuits and Systems (ISCAS), Proceedings of 2017 IEEE International Symposium on. IEEE,2017, pp. 1-4

(6) D. Liu, S. Yin, L. Liu, and S. Wei. Exploiting outer loop parallelism of nested loop on coarse-grained reconfigurable architectures. Field-Programmable Custom Computing Machines (FCCM), 2014 IEEE 22nd Annual International Symposium on, vol., no., pp.32,32, 11-13 May 2014. ^[1] 

授權發明專利

（1）尹首一；劉大江；劉雷波；魏少軍，可重構處理器循環映射優化方法，中國專利201310066541.X，2013

（2）尹首一；劉大江；劉雷波；魏少軍，面向可重構陣列的多參數融合性能建模方法，中國專利201310156766.4，2013

（3）劉大江；任高鋒；李駪駪，基於VANET的採礦系統，中國專利2015100758042，2015

（4）劉大江；李駪駪；任高峯，採礦系統的調度方法和系統，中國專利201510246144X，2015 ^[1] 

1. 國家自然科學基金青年基金，61804017，軟件定義硬件中數據密集型應用的高性能映射技術研究，2019/01 - 2021/12，在研，主持

2. CCF-騰訊犀牛鳥基金，面向數據密集型應用的可重構處理器高性能映射技術研究，2018-2019，在研，主持

3. 十二五863計劃信息技術領域重點“面向通用計算的可重構處理器關鍵技術研究”，2012AA012701，2012-2015，已結題，主研 ^[1]