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sSSE3

鎖定
SSE3是Intel命名的SSE3指令集的擴充,不使用新的號碼是因為SSSE3比較像是加強版的SSE3,以至於推出SSSE3之前,SSE4的定義容易被混淆。在公開Intel的Core微架構的時候,SSSE3出現在Xeon 5100與Intel Core 2移動版與桌面型處理器上。
中文名
sSSE3
外文名
Supplemental Streaming SIMD Extensions 3
類    屬
 SSE3 指令集的擴充
新指令
32 個

sSSE3定義

SSSE3 (S
sSSE3 sSSE3
upplemental Streaming SIMD Extensions 3)是 Intel 命名的 SSE3 指令集的擴充,不使用新的號碼是因為 SSSE3 只是加強版的 SSE3,以至於推出 SSSE3 之前,SSE4 的定義容易被混淆。在公開 Intel 的 Core 微架構的時候,SSSE3 於2006年7月首次裝載在 Xeon 5100 與 Intel Core 2 移動版與桌面型處理器上。

sSSE3指令集

SSE3裝載了用一個命令一口氣處理複數個數據的“SIMD”的處理方式,特別在處理語音和動畫關聯上能夠高速地發揮力量。SSSE3是在SSE3命令的基礎上又添加了32個新命令的產品,其原名為TNI,是SSE4指令集的子集,包含有13條命令。SSSE3也是比較先進的指令集
SSSE3 包含了 16 個新的不同於 SSE3 的指令。每一個都能夠運作於 64 位元的 MMX 暫存器或是 128 位元 XMM 暫存器之中。因此,有些 Intel 的文件表示有 32 個新指令。之前的 SIMD 指令由舊排到新依序是 MMX3DNow!(AMD 開發的)、SSE、3DNow! Professional、SSE2與SSE3。
還沒有確定正式名稱為SSSE3的時候,其編碼名稱為TNI,被預測正式名稱為“SSE4”,但結果被定為SSSE3,SSE4預定被使用於下一代微處理器中。
SSSE3指令集增強了CPU的多媒體、圖形圖象處理、多媒體編碼、整數運算和Internet等方面的處理能力。

sSSE3處理器

Intel:
Xeon 5100 系列
Xeon 5300 系列
Xeon 3000 系列
Core i7
Core i5
Pentium Dual-Core
Celeron 4xx 的 Conroe-L
Celeron Dual Core 系列
Celeron M 500 系列
VIA

sSSE3新增的指令

In the table below, satsw(X) (read as 'saturate to signed word')takes a signed integer X, and converts it to -32768 if it's less than-32768, to +32767 if it's greater than 32767, and leaves it unchangedotherwise. As normal for the Intel architecture, bytes are 8 bits,words 16 bits, and dwords 32 bits; 'register' refers to an MMX or XMMvector register.
PSIGNB, PSIGNW, PSIGND
Packed Sign
Negate the elements of a register of bytes, words or dwords if thesign of the corresponding elements of another register is negative.
PABSB, PABSW, PABSD
Packed Absolute Value
Fill the elements of a register of bytes, words or dwords with the absolute values of the elements of another register
PALIGNR
Packed Align Right
take two registers, concatenate their values, and pull out aregister-length section from an offset given by an immediate valueencoded in the instruction.
PSHUFB
Packed Shuffle Bytes
takes registers of bytes A = [a0 a1 a2 ...] and B = [b0 b1 b2 ...] and replaces A with [ab0 ab1 ab2 ...]; except that it replaces the ith entry with 0 if the top bit of bi is set.
PMULHRSW
Packed Multiply High with Round and Scale
treat the sixteen-bit words in registers A and B as signed 15-bitfixed-point numbers between -1 and 1 (eg 0x4000 is treated as 0.5 and0xa000 as -0.75), and multiply them together with correct rounding.
PMADDUBSW
Multiply and Add Packed Signed and Unsigned Bytes
Take the bytes in registers A and B, multiply them together, addpairs, signed-saturate and store. IE [a0 a1 a2 ...] pmaddubsw [b0 b1 b2...] = [satsw(a0b0+a1b1) satsw(a2b2+a3b3) ...]
PHSUBW, PHSUBD
Packed Horizontal Subtract (Words or Doublewords)
takes registers A = [a0 a1 a2 ...] and B = [b0 b1 b2 ...] and outputs [a0-a1 a2-a3 ... b0-b1 b2-b3 ...]
PHSUBSW
Packed Horizontal Subtract and Saturate Words
like PHSUBW, but outputs [satsw(a0-a1) satsw(a2-a3) ... satsw(b0-b1) satsw(b2-b3) ...]
PHADDW, PHADDD
Packed Horizontal Add (Words or Doublewords)
takes registers A = [a0 a1 a2 ...] and B = [b0 b1 b2 ...] and outputs [a0+a1 a2+a3 ... b0+b1 b2+b3 ...]
PHADDSW
Packed Horizontal Add and Saturate Words
like PHADDW, but outputs [satsw(a0+a1) satsw(a2+a3) ... satsw(b0+b1) satsw(b2+b3) ...]