C/A碼

2個移位寄存器在每週日子夜零時，在置“1”脈衝作用下全處於1狀態，同時在碼率1.023MHZ下，2個移位寄存器分別產生碼長為N=2^10-1=1023，週期為1ms的2個M序列G1（t）和G2（t）。G2（t）序列經過相位選擇器，輸入一個與G2（t）平移等價的M序列，然後與G1（t）模二相加，得到C/A碼.

C/A碼的碼元寬度較大。假設兩個序列的碼元對其誤差為碼寬的1/10~1/100，則此時相應的測距誤差為29.3~2.93m。隨着現代科學技術的發展，使得測距分辨率大大提高。一般最簡單的導航接收機的偽距測量分辨率達到0.1m。

GPS系統中P碼的捕獲通常是利用C/A碼來完成的,用户首先捕獲到C/A碼,然後利用C/A碼調製的導航電文中的握手字(HOW-handover word)所提供的P碼信息對P碼進行捕獲。由於P碼在戰爭中顯得十分重要,而且C/A碼在民用中也發揮了很重要的作用,所以研究並實現C/A碼具有一定的實際價值。

library ieee;

use ieee.std_logic_1164.all;

entity LFSR_A is

generic(cycleA0:integer:=26;

cycleA3:integer:=4;

width:integer:=1);

port(

Clk:in std_logic;

Enable:in std_logic;

Fill_En:in std_logic;

New_Fill:in std_logic_vector(width -1 downto 0);

DelayA0:out std_logic_vector(width -1 downto 0));

end LFSR_A;

architecture LFSR_A_ARCH of LFSR_A is

signal Date_In_A:STD_LOGIC_VECTOR(width -1 downto 0);

signal DelayA3:STD_LOGIC_VECTOR(width -1 downto 0);

signal DelayA0_int:STD_LOGIC_VECTOR(width -1 downto 0);

type my_type is array(0 to cycleA0 -1) of

std_logic_vector(width -1 downto 0);

signal int_sigA0:my_type;

type my_type2 is array (0 to cycleA3 -1) of

std_logic_vector(width -1 downto 0);

signal int_sigA3:my_type2;

begin

main:process(Clk)

begin

if Clk'event and Clk ='1' then

if (Enable='1') then

int_sigA0<=Date_In_A & int_sigA0(0 to cycleA0 -2);

int_sigA3<=Date_In_A & int_sigA3(0 to cycleA3 -2);

end if;

if (Fill_En='0') then Date_In_A<=DelayA3 xor DelayA0_int;

else Date_In_A<=New_Fill;

end if;

end if;

end process main;

delayA0_int<=int_sigA0(cycleA0 -1);

delayA3<=int_sigA3(cycleA3 -1);

delayA0<=delayA0_int;

end LFSR_A_ARCH;

library ieee;

use ieee.std_logic_1164.all;

entity LFSR_B is

generic (cycleB0:integer:=26;

cycleB20:integer:=21;

width:integer:=1);

port(

Clk:in std_logic;

Enable:in std_logic;

Fill_En:in std_logic;

New_Fill:in std_logic_vector(width -1 downto 0);

DelayB0:out std_logic_vector(width -1 downto 0)

);

end LFSR_B;

architecture LFSR_B_ARCH of LFSR_B is

signal Data_In_B:std_logic_vector(width -1 downto 0);

signal DelayB20:std_logic_vector(width -1 downto 0);

signal DelayB0_int:std_logic_vector(width -1 downto 0);

type my_type is array (0 to cycleB0 -1) of

std_logic_vector(width -1 downto 0);

signal int_sigB0:my_type;

type my_type2 is array(0 to cycleB20 -1) of

std_logic_vector(width -1 downto 0);

signal int_sigB20:my_type2;

begin

main:process(Clk)

begin

if Clk'event and Clk='1' then

if (Enable='1') then

int_sigB0<=Data_In_B & int_sigB0(0 to cycleB0 -2);

int_sigB20<=Data_In_B & int_sigB20(0 to cycleB20 -2);

end if;

if (Fill_En='0') then Data_In_B<=DelayB20 xor DelayB0_int;

else Data_In_B<=New_Fill;

end if;

end if;

end process main;

delayB0_int<=int_sigB0(cycleB0 -1);

delayB20<=int_sigB20(cycleB20 -1);

delayB0<=delayB0_int;

end LFSR_B_ARCH;

library ieee;

use ieee.std_logic_1164.all;

entity Gold_Code is

generic (width:integer:=1);

port(

Clock:in std_logic;

Enable:in std_logic;

Fill_En_A:in std_logic;

Fill_En_B:in std_logic;

Rst:in std_logic;

New_Fill_A:in std_logic_vector(width -1 downto 0);

New_Fill_B:in std_logic_vector(width -1 downto 0);

Gold_Code:out std_logic_vector(width -1 downto 0)

);

end Gold_Code;

architecture Gold_Code_Arch of Gold_Code is

component LFSR_A port

(Clk:in std_logic;

Enable:in std_logic;

Fill_En:in std_logic;

New_Fill:in std_logic_vector(width -1 downto 0);

delayA0:out std_logic_vector(width -1 downto 0));

end component;

component LFSR_B port

(Clk:in std_logic;

Enable:in std_logic;

Fill_En:in std_logic;

New_Fill:in std_logic_vector(width -1 downto 0);

delayB0:out std_logic_vector(width -1 downto 0));

end component;

signal DelayA_top:std_logic_vector(width -1 downto 0);

signal DelayB_top:std_logic_vector(width -1 downto 0);

begin

U0:LFSR_A port map (Clk=>Clock,Enable=>Enable,

Fill_En=>Fill_En_A,

New_Fill=>New_Fill_A,

delayA0=>delayA_top);

U1:LFSR_B port map (Clk=>Clock,Enable=>Enable,

Fill_En=>Fill_En_B,

New_Fill=>New_Fill_B,

delayB0=>delayB_top);

Gold_Code<=delayB_top xor delayA_top;

end Gold_Code_Arch;